1. Field of the Invention
This invention relates to semiconductor processing techniques. Specifically, the present invention relates to an improved anti-fuse semiconductor device via formation method.
2. Prior Art
In order to form anti-fuse semiconductor devices, several processing steps are performed. First, well known CMOS processing steps are performed up to the deposition of an inter-metal oxide over a first metal or "metal 1" layer. Next, a second metallic layer is deposited and etched as desired over the inter-metal oxide layer to form a conductive layer or "straps." An oxide layer is then deposited over the straps. After the deposition of the oxide layer, vias are formed extending completely through the oxide layer to the underlying straps.
A layer of amorphous silicon is then deposited over the oxide layer and into the vias formed therethrough. However, in prior art anti-fuse semiconductor device processing methods, notching or "cusping" of the amorphous silicon layer occurs within the vias. That is, as the amorphous silicon is deposited into the vias, the thickness of amorphous silicon is much greater at the center of the vias than at the corners of the vias. As a result, unwanted cusps or crevices in the layer of amorphous silicon are produced in the corner regions of the vias.
The production of cusps in the layer of amorphous silicon deposited into the vias is deleterious to the integrity of anti-fuse semiconductor devices. Specifically, the breakdown or programming voltage of the anti-fuse devices is dependent upon, among other things, the thickness of the layer of amorphous silicon within the "fuse" vias. That is, during a subsequent processing step, a third metallic layer is deposited over the layer of amorphous silicon. The cusps allow the metallic layer to closely approach the underlying straps. Thus, when voltage is applied to the devices, a much lower breakdown or programming voltage than is desired causes the anti-fuse device to become conductive.
In an attempt to prevent the third metallic layer from descending into the cusps in the amorphous silicon layer at the corner of the fuse vias, prior art anti-fuse semiconductor device formation techniques employ additional processing steps. In the prior art, after the deposition of the layer of amorphous silicon, but before the deposition of the third metallic layer, an additional oxide or "spacer oxide" layer is deposited over the amorphous silicon and into the vias. The spacer oxide fills the cusps present in the amorphous silicon at the corners of the vias. The spacer oxide is then removed or etched from everywhere except the cusps in the amorphous silicon at the corner of the fuse vias. In so doing, when the third metallic layer is subsequently deposited over the amorphous silicon and into the fuse vias, the spacer oxide present in the cusps prevents the metal from filling the cusps.
However, in addition to the increased cost and decreased cycle time associated with the deposition and etching steps of the spacer oxide, other problems are also created by the spacer oxide steps. For example, in certain vias such as strap vias, which formed in close proximity to and at the same time as the fuse vias, the layer of amorphous silicon is completely removed therefrom. Thus, when the third metallic layer is deposited, direct contact is made between the third metallic layer deposited into the strap vias and the underlying straps. Unfortunately, the spacer oxide step used to fill the amorphous silicon cusps of the fuse vias can also reduce or even prevent contact between the third metallic layer and the underlying straps in neighboring strap vias. That is, in the prior art the amorphous silicon is etched from the unwanted areas including the strap vias using an etch having high amorphous silicon selectivity. As a result, other material such as the oxide used for the spacer oxide will not be removed or etched by the amorphous silicon etch. Rather, the spacer oxide will act as a barrier and prevent etching of the underlying amorphous silicon in the cusp areas of the strap vias. Thus, unwanted amorphous silicon residue or "dog ears" remain in the strap vias after the amorphous silicon etch step. Consequently, when the third metallic layer is deposited into the strap vias, the dog ears prevent the metallic layer from reaching and forming electrical connections to the underlying straps.
Therefore, prior art anti-fuse semiconductor device formation methods employ numerous steps resulting in increased cost and decreased cycle time in an attempt to deal with the problem of cusping of the amorphous silicon layer within the corners of the fuse vias. Furthermore, the prior art steps also generate unwanted residual amorphous silicon within the link or strap vias. As a result, electrical connections within the strap vias between the third metallic layer and the underlying straps are obstructed.
Thus, the need has arisen for an anti-fuse semiconductor device via, and a method for forming such a via, which allows for the deposition of a uniform layer of amorphous silicon without cusping of the amorphous silicon layer within the via, which reduces the amount of required process steps, does not require the deposition of a spacer oxide, and which does not produce substantial amorphous silicon residue in strap vias.